Data packets that come across a networking switch may be sampled for a given number of packets. For example, every 200 packets may be sampled, and this sampled value may then be sent to another module for processing. In one approach, the sampling signal is generated by using one (1) fixed-width counter per switch port, and the counter is replicated two (2) times for every port in the switch product. This type of implementation takes a significant amount of resources on the chip, particularly as the number of ports increases, and this typically increases the cost of the final product.
In another approach that use a pipelined design, counter resources may be shared and this leads to some savings in chip resources. However, this approach is not able to generate a sample signal after the strobe generation in a timely manner for some applications, since the sharing of counter resources introduces latency in the design. This can result in an inaccurate count of the packets that are sampled.
Therefore, the current technologies are limited to particular capabilities and suffer from various constraints.